On November 1, the Packaging & Testing Branch of the China Semiconductor Industry Association announced that the 2026 Semiconductor Packaging, Testing Technology and Market Annual Conference (the 24th edition) will be held from November 4 to 6 at the Fengda International Hotel in Nanjing. Guided by the China Semiconductor Industry Association and hosted by its Packaging & Testing Branch, organized by Tianshui Huatian Technology together with Future Semiconductor and co-organized by JCET, Tongfu Microelectronics and Zhongkexin IC, the conference is expected to draw around 2,000 participants under the theme “AI Sets Out, Packaging Builds the Chip Foundation.” Huawei, Loongson, Xiaomi Auto, ByteDance, Cambricon, YMTC and other key players across the industry chain have confirmed their attendance.
Over the two-day program, heavyweight speakers from Huatian Technology, JCET, Tongfu Microelectronics, Biren, BOE and Yuntian Semiconductor — leaders across packaging & testing, chip design, glass substrates and TGV technology — will exchange views on the latest directions in advanced packaging through a main forum, special-topic reports and supply-demand matchmaking sessions. The published attendee list also includes UNISOC, Goke, Moore Threads, Hygon, ZTE, NIO, Alibaba and Empyrean, alongside Tsinghua University, Southeast University and Nanjing University — in effect the full chain from packaging, design and equipment to EDA, automakers and internet demand-side companies, signaling a strong supply-demand matchmaking agenda.
From an industry-landscape perspective, the conference putting “AI” and “packaging” directly into its theme confirms the rising status of advanced packaging in the AI chip era: as Chiplet partitioning, 2.5D/3D stacking, glass substrates and TGV through-hole technology become standard paths for high-compute chips, the packaging and testing stage is shifting from a traditional labor-intensive back-end process into a decisive factor in AI chip performance, yield and cost. Earlier reports that TSMC plans to raise advanced packaging prices amid tight CoWoS capacity already pointed to a tight supply-demand balance; the collective presence of China’s packaging & testing leaders together with equipment and materials suppliers, plus deep participation from end-demand players such as Huawei and Xiaomi Auto, signals that the domestic advanced packaging ecosystem is moving from “capacity catch-up” toward “co-creating technology roadmaps.”
For board-level and system-level vendors like Junyi Microelectronics, the deepening domestic advanced packaging chain is a hidden guarantee of product stability: the Rockchip SoCs behind the J-3568/J-3576/J-3588 core boards and K-series edge AI motherboards, and the memory and power devices inside the AI-BOX-3588 edge computing host, all depend directly on packaging process maturity for their performance, power efficiency and supply cadence; the IPC-i5-1235U industrial mini PC and touch-panel all-in-one product lines likewise benefit from the die-size and cost optimizations enabled by advanced packaging. Junyi Microelectronics will keep tracking the process and capacity signals released at the conference, converting upstream technology dividends into competitive advantages in stability, supply certainty and cost-performance across its system products.
Source: https://www.ithome.com/1/020/803.htm (November 1, 2026)